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FEATURES 20 MSPS Correlated Double Sampler (CDS) 4 dB 6 dB Variable CDS Gain with 6-Bit Resolution 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) Low Noise Clamp Circuits Analog Preblanking Function 12-Bit 20 MSPS A/D Converter Auxiliary Inputs with VGA and Input Clamp 3-Wire Serial Digital Interface 3 V Single Supply Operation Low Power: 65 mW @ 2.7 V Supply 48-Lead LQFP Package APPLICATIONS Digital Still Cameras Digital Video Camcorders PC Cameras
Complete 12-Bit 20 MSPS CCD Signal Processor AD9844A
PRODUCT DESCRIPTION
The AD9844A is a complete analog signal processor for CCD applications. It features a 20 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The AD9844A's signal chain consists of an input clamp, correlated double sampler (CDS), digitally controlled variable gain amplifier (VGA), black level clamp, and 12-bit A/D converter. Additional input modes are provided for processing analog video signals. The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjustment, black level adjustment, input configuration, and power-down modes. The AD9844A operates from a single 3 V power supply, typically dissipates 78 mW, and is packaged in a 48-lead LQFP.
FUNCTIONAL BLOCK DIAGRAM
PBLK AVDD AVSS CLPOB
DRVDD 4dB 6dB 2dB~36dB CCDIN CDS 2:1 MUX CLP CLPDM 10 AUX1IN 2:1 MUX AUX2IN CLP INTERNAL REGISTERS DVDD BUF 6 8 BANDGAP REFERENCE VRT VRB VGA 12-BIT ADC 12 DOUT CLP DRVSS
OFFSET DAC
INTERNAL BIAS
CML
AD9844A
SL
DIGITAL INTERFACE
INTERNAL TIMING
DVSS
SCK
SDATA
SHP
SHD
DATACLK
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD9844A-SPECIFICATIONS
GENERAL SPECIFICATIONS (T
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION Normal Operation Power-Down Modes Fast Recovery Mode Standby Total Power-Down MAXIMUM CLOCK RATE A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage Data Output Coding VOLTAGE REFERENCE Reference Top Voltage (VRT) Reference Bottom Voltage (VRB)
Specifications subject to change without notice.
MIN
to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
Min -20 -65 2.7 Typ Max +85 +150 3.6 Unit C C V
(Specified Under Each Mode of Operation) 45 5 1 20 12 0.5 12 2.0 Straight Binary 2.0 1.0 1.0 mW mW mW MHz Bits LSB Bits Guaranteed V
V V
DIGITAL SPECIFICATIONS (DRVDD = 2.7 V, C = 20 pF unless otherwise noted.)
L
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage, IOH = 2 mA Low Level Output Voltage, IOL = 2 mA
Specifications subject to change without notice.
Symbol VIH VIL IIH IIL CIN VOH VOL
Min 2.1
Typ
Max
Unit V V A A pF V V
0.6 10 10 10 2.2 0.5
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AD9844A CCD-MODE SPECIFICATIONS
Parameter POWER CONSUMPTION
MAXIMUM CLOCK RATE CDS Allowable CCD Reset Transient 1 Max CCD Black Pixel Amplitude 1 Max Input Range Before Saturation 1 Max Input Range Before Saturation Max Input Range Before Saturation Max Output Range Gain Resolution Gain Range (Two's Complement Coding) Min Gain (CDS Gain Register Code 32) Medium Gain (CDS Gain Code 63) Max Gain (CDS Gain Code 31) VARIABLE GAIN AMPLIFIER (VGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Low Gain (VGA Register Code 91) Max Gain (VGA Code 1023) BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Min Clamp Level Max Clamp Level SYSTEM PERFORMANCE Gain Accuracy, VGA Code 91 to 1023 Peak Nonlinearity, 500 mV Input Signal Peak Nonlinearity, 800 mV Input Signal Total Output Noise Power Supply Rejection (PSR) POWER-UP RECOVERY TIME From Fast Recovery Mode From Reference Standby Mode From Total Shutdown Mode From Power-Off Condition -0.5 0.1 0.4 0.6 40 0.1 1 3 15 20 500 200 1.0 1.5 0.5 1.6 64 -2 4 10 1.6 2.0 1024 Guaranteed 2 36 256 0 255 +0.5
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 20 MHz, unless otherwise noted.)
Min Typ
78
Max
Unit
mW MHz mV mV V p-p V p-p V p-p V p-p Steps dB dB dB V p-p V p-p Steps
Notes
See TPC 1 for Power Curves
See Input Waveform in Note 1 With 4 dB CDS Gain With -2 dB CDS Gain With 10 dB CDS Gain At Any CDS Gain Setting See Figure 12 for CDS Gain Curve 4 dB Is Default with CDS Gain Disabled
dB dB Steps
See Figure 13 for VGA Gain Curve See Figure 13 for Gain Equations
Measured at ADC Output LSB LSB dB % % LSB rms dB ms ms ms ms Specifications Include Entire Signal Chain Use Equations on Page 13 to Calculate Gain 12 dB Gain Applied (4 dB CDS Gain) 8 dB Gain Applied (4 dB CDS Gain) AC Grounded Input, 6 dB Gain Applied Measured with Step Change on Supply Clocks Must Be Applied, as in Figures 5 and 6
NOTES 1 Input Signal Characteristics defined as follows, with 4 dB CDS gain:
500mV TYP RESET TRANSIENT 200mV MAX OPTICAL BLACK PIXEL
1V MAX INPUT SIGNAL RANGE
Specifications subject to change without notice.
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AD9844A-SPECIFICATIONS
AUX1-MODE SPECIFICATIONS (T
Parameter POWER CONSUMPTION MAXIMUM CLOCK RATE INPUT BUFFER Gain Max Input Range VGA Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain
Specifications subject to change without notice.
MIN
to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
Min Typ 60 20 0 1.0 2.0 1023 0 36 Max Unit mW MHz dB V p-p V p-p Steps dB dB
AUX2-MODE SPECIFICATIONS
Parameter POWER CONSUMPTION MAXIMUM CLOCK RATE INPUT BUFFER VGA Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain ACTIVE CLAMP Clamp Level Resolution Clamp Level (Measured at ADC Output) Min Clamp Level Max Clamp Level
Specification subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
Min Typ 60 20 (Same as AUX1-MODE) 2.0 512 0 18 256 0 255 V p-p Steps dB dB Steps LSB LSB Max Unit mW MHz
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AD9844A TIMING SPECIFICATIONS
Parameter SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period DATACLK High/Low Pulsewidth SHP Pulsewidth SHD Pulsewidth CLPDM Pulsewidth CLPOB Pulsewidth1 SHP Rising Edge to SHD Falling Edge SHP Rising Edge to SHD Rising Edge Internal Clock Delay Inhibited Clock Period DATA OUTPUTS Output Delay Output Hold Time Pipeline Delay SERIAL INTERFACE Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read
(CL = 20 pF, fSAMP = 20 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7. Serial Timing in Figures 8-10.)
Symbol tCONV tADC tSHP tSHD tCDM tCOB tS1 tS2 tID tINH tOD tH Min 48 20 7 7 4 2 0 20 10 14.5 7.6 9 16 Typ 50 25 12.5 12.5 10 20 12.5 25 3.0 Max Unit ns ns ns ns Pixels Pixels ns ns ns ns ns ns Cycles MHz ns ns ns ns ns
7.0
fSCLK tLS tLH tDS tDH tDV
10 10 10 10 10 10
NOTES 1 Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS With Respect To Min Max AVSS DVSS DRVSS DRVSS DVSS DVSS DVSS AVSS AVSS -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 +3.9 +3.9 +3.9 DRVDD + 0.3 DVDD + 0.3 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 150 300
ORDERING GUIDE
Model
Unit V V V V V V V V V C C
Temperature Range -20C to +85C
Package Description Thin Plastic Quad Flatpack (LQFP)
Package Option ST-48
Parameter AVDD1, AVDD2 DVDD1, DVDD2 DRVDD Digital Outputs SHP, SHD, DATACLK CLPOB, CLPDM, PBLK SCK, SL, SDATA VRT, VRB, CMLEVEL BYP1-4, CCDIN Junction Temperature Lead Temperature (10 sec)
AD9844AJST
THERMAL CHARACTERISTICS
Thermal Resistance 48-Lead LQFP Package JA = 92C
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9844A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD9844A
PIN CONFIGURATION
THREE-STATE DVSS DVDD2
SDATA
SL NC STBY NC
48 47 46 45 44 43 42 41 40 39 38 37
(LSB) D0 D1 D2 D3
1 2 3 4
VRT CML
36 35 34
SCK
VRB
PIN 1 IDENTIFIER
AUX1IN
AVSS AUX2IN 33 AVDD2
D4 5 D5 6 D6 7 D7 8 D8 9 D9 10 D10 11 (MSB) D11 12 NC = NO CONNECT
AD9844A
TOP VIEW (Not to Scale)
32 31 30 29 28
BYP4 NC CCDIN
BYP2 BYP1 27 AVDD1 AVSS AVSS
26 25 13 14 15 16 17 18 19 20 21 22 23 24
DRVSS DVSS DATACLK DVDD1
CLPDM
DVSS PBLK CLPOB SHP
PIN FUNCTION DESCRIPTIONS
Pin Number
1-12 13 14 15, 18, 24, 41 16 17 19 20 21 22 23 25, 26, 35 27 28 29 30 31 32 33 34 36 37 38 39 40 42 43 44 45 46 47 48
Name
D0-D11 DRVDD DRVSS DVSS DATACLK DVDD1 PBLK CLPOB SHP SHD CLPDM AVSS AVDD1 BYP1 BYP2 CCDIN NC BYP4 AVDD2 AUX2IN AUX1IN CML VRT VRB DVDD2 THREE-STATE NC STBY NC SL SDATA SCK
Type
DO P P P DI P DI DI DI DI DI P P AO AO AI NC AO P AI AI AO AO AO P DI NC DI NC DI DI DI
DRVDD
Description
Digital Data Outputs Digital Output Driver Supply Digital Output Driver Ground Digital Ground Digital Data Output Latch Clock Digital Supply Preblanking Clock Input Black Level Clamp Clock Input CDS Sampling Clock for CCD's Reference Level CDS Sampling Clock for CCD's Data Level Input Clamp Clock Input Analog Ground Analog Supply Internal Bias Level. Decoupling Internal Bias Level Decoupling Analog Input for CCD Signal Leave Floating or Decouple to Ground with 0.1 F Internal Bias Level Decoupling Analog Supply Analog Input Analog Input Internal Bias Level Decoupling A/D Converter Top Reference Voltage Decoupling A/D Converter Bottom Reference Voltage Decoupling Digital Supply Digital Output Disable. Active High May be tied High or Low. Should not be left floating. Standby Mode, Active High. Same as Serial Interface Standby Mode Internally Not Connected. May be Tied High or Low Serial Digital Interface Load Pulse Serial Digital Interface Data Serial Digital Interface Clock
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
DVSS
SHD
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AD9844A
DEFINITIONS OF SPECIFICATIONS
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating conditions.
PEAK NONLINEARITY
chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC Full Scale/2N codes) when N is the bit resolution of the ADC. For the AD9844A, 1 LSB is 0.5 mV.
POWER SUPPLY REJECTION (PSR)
Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9844A from a true straight line. The point used as "zero scale" occurs 1/2 LSB before the first code transition. "Positive full scale" is defined as a Level 1, 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC's full-scale range.
TOTAL OUTPUT NOISE
The PSR is measured with a step change applied to the supply pins. This represents a very high-frequency disturbance on the AD9844A's power supply. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage.
INTERNAL DELAY FOR SHP/SHD
The internal delay (also called aperture delay) is the time delay that occurs from when a sampling edge is applied to the AD9844A until the actual sample of the input signal is held. Both SHP and SHD sample the input signal during the transition from low to high, so the internal delay is measured from each clock's rising edge to the instant the actual internal sample is taken.
The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB, and represents the rms noise level of the total signal
EQUIVALENT INPUT CIRCUITS
DVDD
ACVDD
330
DVSS
ACVSS
ACVSS
Figure 1. Digital Inputs--SHP, SHD, DATACLK, CLPOB, CLPDM, HD, VD, PBLK, SCK, SL
DVDD
Figure 3. CCDIN (Pin 30)
DRVDD
DATA
DVDD DATA IN
DVDD
THREESTATE
DOUT
DATA OUT
330
RNW
DVSS
DVSS
DVSS
Figure 4. SDATA (Pin 47)
DVSS DRVSS
Figure 2. Data Outputs
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AD9844A-Typical Performance Characteristics
100
15
90
POWER DISSIPATION - mW
80
OUTPUT NOISE - LSB
VDD = 3.3V
10
70
VDD = 3.0V
60
VDD = 2.7V
5
50
40 5 10 15 SAMPLE RATE - MHz 20
0 0 200 400 600 VGA GAIN CODE - LSB 800 1000
TPC 1. Power vs. Sample Rate
TPC 3. Output Noise vs. VGA Gain
0.5
0.25
0
-0.25
-0.5 0 500 1000 1500 2000 2500 3000 3500 4000
TPC 2. Typical DNL Performance
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AD9844A
CCD-MODE AND AUX-MODE TIMING
CCD SIGNAL
N
N+1
N+2
N+9
N+10
tID
SHP
tID
tS1
SHD
tS2
tCP
tINH
DATACLK
tOD
OUTPUT DATA N-10 N-9
tH
N-8 N-1 N
NOTES: 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
Figure 5. CCD-Mode Timing
EFFECTIVE PIXELS
OPTICAL BLACK PIXELS
HORIZONTAL BLANKING
DUMMY PIXELS
EFFECTIVE PIXELS
CCD SIGNAL
CLPOB
CLPDM
PBLK
OUTPUT DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA
DUMMY BLACK
EFFECTIVE DATA
NOTES: 1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB. 2. PBLK SIGNAL IS OPTIONAL. 3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.
Figure 6. Typical CCD-Mode Line Clamp Timing
N VIDEO SIGNAL
N+9 N+1 N+8 N+2
tID tCP
DATACLK
tOD
OUTPUT DATA N-10 N-9
tH
N-8 N-1 N
Figure 7. AUX-Mode Timing
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AD9844A
SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION Table I. Internal Register Map
Register Name
Operation VGA Gain Clamp Level Control CDS Gain
Address A0 A1 A2
0 1 0 1 0 0 0 1 1 0 0 0 0 0 1
D0
D1
D2
D3
Data Bits D4 D5
D6
D7
1**
D8
0*
D9
0* MSB
D10
0* X X X X
Channel Select CCD/AUX LSB LSB 0* LSB 0*
Power-Down Modes
Software OB Clamp 0* Reset On/Off
MSB 0* CDS Gain Clock Polarity Select for On/Off SHP/SHD/CLP/DATA MSB X 0* X
X 0* X
X ThreeState X
*Internal use only, must be set to zero. **Should be set to one.
RNW SDATA 0 A0 A1 A2 TEST 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
tDS
SCK
tDH
tLS
SL NOTES: 1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK. 2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION. 3. TEST BIT = INTERNAL USE ONLY. MUST BE SET LOW. 4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
tLH
Figure 8. Serial Write Operation
RNW SDATA 1 A0 A1 A2
TEST 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
tDS
SCK
tDH
tDV
tLS
SL
tLH
NOTES: 1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION. 2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW. 3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON SCK FALLING EDGES.
Figure 9. Serial Readback Operation
RNW A0 SDATA 0 0
A1 0 0 0 D0 D1
11 BITS OPERATION D2 D3 ... D10 D0 D1
10 BITS AGC GAIN D2 D3 ... D9
8 BITS CLAMP LEVEL D0 ... D7
10 BITS CONTROL D0 ... D9
SCK 1 SL 2 3 4 5 6 7 8 9
... 16 17 18 19 20
... 26 27
... 34 35
... 44
...
NOTES: 1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING ONE ADDRESS AT A TIME. 2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER. 3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.
Figure 10. Continuous Serial Write Operation to Multiple Registers
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AD9844A
Table II. Operation Register Contents (Default Value x000) D10 0* D9 0* D8 0* D7 1** D6 0* Optical Black Clamp D5 0 Enable Clamping 1 Disable Clamping Reset D4 0 Normal 1 Reset All Registers to Default Power-Down Modes D3 D2 0 0 1 1 0 1 0 1 Normal Power Fast Recovery Standby Total Power-Down Channel Selection D1 D0 0 0 1 1 0 1 0 1 CCD-Mode AUX1-Mode AUX2-Mode Test Only
*Must be set to zero. **Set to one.
Table III. VGA Gain Register Contents (Default Value x096) D10 X MSB D9 0 D8 0 D7 0 D6 1 D5 0 D4 1 D3 1 D2 1 D1 1 LSB D0 1 Gain (dB) 2.0
* * *
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
* * *
35.965 36.0
Table IV. Clamp Level Register Contents (Default Value x080) D10 X D9 X D8 X MSB D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 1 LSB D0 0 1 0 Clamp Level (LSB) 0 1 2
* * *
1 1 1 1 1 1 1 0
* * *
254
1
1
1
1
1
1
1
1
255
Table V. Control Register Contents (Default Value x000) D10 Data Out D9 D8 D7 DATACLK D6 CLP/PBLK D5 SHP/SHD D4 CDS Gain D3 D2 D1 D0
X
0 Enable 1 Three-State
0*
0*
0 Rising Edge Trigger 1 Falling Edge Trigger
0 Active Low 1 Active High
0 Active Low 1 Active High
0 Disabled** 0* 1 Enabled
0*
0*
*Must be set to zero. **When D3 = 0 (CDS Gain Disabled), the CDS Gain Register is fixed at -4 dB (Code 63 dec).
Table VI. CDS Gain Register Contents (Default Value x000) D10 X D9 X D8 X D7 X D6 X MSB D5 0 D4 0 D3 0 D2 0 D1 0 LSB D0 0 Gain (dB) * +4.3
* * *
0 1 1 0 1 0 1 0 1 0 0 0
* * *
+10.0 -2.0
* * * 1 1 1 1 1 1
*Control Register Bit D3 must be set high for the CDS Gain Register to be used.
* * * +4.0
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AD9844A
DC RESTORE CDS GAIN REGISTER 6 -2dB TO +10dB 0.1 F CCDIN CDS INPUT OFFSET CLAMP 10 CLPDM VGA GAIN REGISTER 8-BIT DAC OPTICAL BLACK CLAMP CLPOB VGA 2dB TO 36dB INTERNAL VREF 2V FULL SCALE 12-BIT ADC 12 DOUT
DIGITAL FILTERING
0 TO 255 LSB 8 CLAMP LEVEL REGISTER
Figure 11. CCD-Mode Block Diagram
CIRCUIT DESCRIPTION AND OPERATION Table VII. Example CDS Gain Settings Max Input Signal 250 mV p-p 500 mV p-p 800 mV p-p 1 V p-p 1.25 V p-p 1.5 V p-p
10
The AD9844A signal processing chain is shown in Figure 11. Each processing step is essential in achieving a high-quality image from the raw CCD pixel data.
DC Restore
Recommended Gain Range 8 to 10 dB 6 to 8 dB 4 to 6 dB 2 to 4 dB 0 to 2 dB -2 to 0 dB
Register Code Range 21 to 31 10 to 21 63 to 10 53 to 63
To reduce the large dc offset of the CCD output signal, a dc-restore circuit is used with an external 0.1 F series-coupling capacitor. This restores the dc level of the CCD signal to approximately 1.5 V, to be compatible with the 3 V single supply of the AD9844A.
Correlated Double Sampler
42 to 53
32 to 42
CDS GAIN - dB
The CDS circuit samples each CCD pixel twice to extract the video information and reject low-frequency noise. The timing shown in Figure 5 illustrates how the two CDS clocks, SHP and SHD, are used to sample the reference level and data level of the CCD signal respectively. The CCD signal is sampled on the rising edges of SHP and SHD. Placement of these two clock signals is critical in achieving the best performance from the CCD. An internal SHP/SHD delay (tID) of 3 ns is caused by internal propagation delays. The CDS stage has a default gain of 4 dB, but uses a unique architecture that allows the CDS gain to be varied. Using the CDS Gain Register, the gain is programmable from -2 dB to +10 dB in 64 steps, using two's complement coding. The CDS Gain curve is shown in Figure 12. To change the gain of the CDS using the CDS Gain Register, the Control Register bit D3 must be set high (CDS Gain Enabled). The default gain setting when bit Control Register Bit D3 is low (CDS Gain Disabled) is 4 dB. See Tables V and VI for more details. A CDS gain of 4 dB provides some front-end signal gain and improves the overall signal-to-noise ratio. This gain setting works very well in most applications, and the CCD-Mode Specifications use this default gain setting. However, the CDS gain may be varied to optimize the AD9844A operation in a particular application. Increased CDS gain can be useful with low output level CCDs, while decreased CDS gain allows the AD9844A to accept CCD signal swings greater than 1 V p-p. Table VII summarizes some example CDS gain settings for different maximum signal swings. The CDS Gain Register may also be used "on the fly" to provide a +6 dB boost or -6 dB attenuation when setting exposure levels. It is best to keep the CDS output level from exceeding 1.5 V~1.6 V. -12-
8
6
4
2
0
-2 32 (100000)
40
48
56
0
8
16
24
31 (011111)
CDS GAIN REGISTER CODE
Figure 12. CDS Gain Curve
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AD9844A
Input Clamp
A line-rate input clamping circuit is used to remove the CCD's optical black offset. This offset exists in the CCD's shielded black reference pixels. Unlike some AFE architectures, the AD9844A removes this offset in the input stage to minimize the effect of a gain change on the system black level, usually called the "gain step." Another advantage of removing this offset at the input stage is to maximize system headroom. Some area CCDs have large black level offset voltages, which, if not corrected at the input stage, can significantly reduce the available headroom in the internal circuitry when higher VGA gain settings are used. Horizontal timing is shown in Figure 6. It is recommended that the CLPDM pulse be used during valid CCD dark pixels. CLPDM may be used during the optical black pixels, either together with CLPOB or separately. The CLPDM pulse should be a minimum of 4 pixels wide.
Variable Gain Amplifier
The optical black clamp loop is used to remove residual offsets in the signal chain, and to track low-frequency variations in the CCD's black level. During the optical black (shielded) pixel interval on each line, the ADC output is compared with a fixed black level reference, selected by the user in the Clamp Level Register. Any value between 0 LSB and 255 LSB may be programmed, with 8-bit resolution. The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input through a D/A converter. Normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. If external digital clamping is used during the post processing, the AD9844A's optical black clamping may be disabled using bit D5 in the Operation Register (see Serial Interface Timing and Internal Register Description section). When the loop is disabled, the Clamp Level Register may still be used to provide programmable offset adjustment. Horizontal timing is shown in Figure 5. The CLPOB pulse should be placed during the CCD's optical black pixels. It is recommended that the CLPOB pulse duration be at least 20 pixels wide to minimize clamp noise. Shorter pulsewidths may be used, but clamp noise may increase, and the loop's ability to track low-frequency variations in the black level will be reduced.
A/D Converter
The VGA stage provides a gain range of 2 dB to 36 dB, programmable with 10-bit resolution through the serial digital interface. Combined with the typical 4 dB gain from the CDS stage, the total gain range for the AD9844A is 6 dB to 40 dB. A gain of 6 dB will match a 1 V input signal with the ADC full-scale range of 2 V. When compared to 1 V full-scale systems (such as ADI's AD9803), the equivalent gain range is 0 dB to 34 dB. The VGA gain curve is divided into two separate regions. When the VGA Gain Register code is between 0 and 511, the curve follows a (1 + x)/(1 - x) shape, which is similar to a "linear-indB" characteristic. From code 512 to code 1023, the curve follows a "linear-in-dB" shape. The exact VGA gain can be calculated for any Gain Register value by using the following two equations: Code Range 0-511 512-1023 Gain Equation (dB) Gain = 20 log10 ([658 + code]/[658 - code]) - 0.35 Gain = (0.0354)(code) - 0.35
The AD9844A uses a high-performance ADC architecture, optimized for high speed and low power. Differential nonlinearity (DNL) performance is typically better than 0.5 LSB, as shown in TPC 2. Instead of the 1 V full-scale range used by the earlier AD9801 and AD9803 products from Analog Devices, the AD9844A's ADC uses a 2 V input range. Better noise performance results from using a larger ADC full-scale range (see TPC 3).
AUX1-Mode
Using these two equations, the actual gain of the AD9844A can be accurately predicted to within 0.5 dB. As shown in the CCD-Mode Specifications, only the VGA gain range from 2 dB to 36 dB is specified. This corresponds to a VGA gain code range of 91 to 1023. The Gain Accuracy specifications also include a CDS gain of 4 dB, for a total gain range of 6 dB to 40 dB.
36
30
For applications that do not require CDS, the AD9844A can be configured to sample ac-coupled waveforms. Figure 14 shows the circuit configuration for using the AUX1 channel input (Pin 36). A single 0.1 F ac-coupling capacitor is needed between the input signal driver and the AUX1IN pin. An onchip dc-bias circuit sets the average value of the input signal to approximately 0.4 V, which is referenced to the midscale code of the ADC. The VGA Gain register provides a gain range of 0 dB to 36 dB in this mode of operation (see VGA Gain Curve, Figure 12). The VGA gains up the signal level with respect to the 0.4 V bias level. Signal levels above the bias level will be further increased to a higher ADC code, while signal levels below the bias level will be further decreased to a lower ADC code.
AUX2-Mode
VGA GAIN - dB
24
18
12
6
0
0
127
255 383 511 639 767 VGA GAIN REGISTER CODE
895
1023
Figure 13. VGA Gain Curve (Gain from CDS Not Included) Optical Black Clamp
For sampling video-type waveforms, such as NTSC and PAL signals, the AUX2 channel provides black level clamping, gain adjustment, and A/D conversion. Figure 15 shows the circuit configuration for using the AUX2 channel input (Pin 34). An external 0.1 F blocking capacitor is used with the on-chip video clamp circuit, to level-shift the input signal to a desired reference level. The clamp circuit automatically senses the most negative portion of the input signal, and adjusts the voltage across the input capacitor. This forces the black level of the input signal to be equal to the value programmed into the Clamp Level register (see Serial Interface Register Description). The VGA provides gain adjustment from 0 dB to 18 dB. The same VGA Gain register is used, but only the 9 MSBs of the gain register are used (see Table VIII.) -13-
REV. 0
AD9844A
0.8V ??V 0.4V 5k 0.1 F INPUT SIGNAL AUX1IN VGA ADC MIDSCALE 0dB TO 36dB
0.4V
0.4V
10 VGA GAIN REGISTER
Figure 14. AUX1 Circuit Configuration
VGA GAIN REGISTER 9 BUFFER VIDEO SIGNAL AUX2IN 0.1 F VIDEO CLAMP CIRCUIT LPF 8 CLAMP LEVEL REGISTER CLAMP LEVEL 0dB TO 18dB
VGA
ADC
Figure 15. AUX2 Circuit Configuration
Table VIII. VGA Gain Register Used for AUX2-Mode
D10 X
MSB D9 0 1
D8 X 0
D7 X 0
D6 X 0
D5 X 0 * * * 1
D4 X 0
D3 X 0
D2 X 0
D1 X 0
LSB D0 X 0
Gain (dB) 0.0 0.0 * * * 18.0
1
1
1
1
1
1
1
1
1
-14-
REV. 0
AD9844A
CCD
VOUT 0.1 F CCDIN REGISTER DATA BUFFER V-DRIVE CCD TIMING CDS/CLAMP TIMING
AD9844A
ADCOUT
DIGITAL OUTPUTS SERIAL INTERFACE
DIGITAL IMAGE PROCESSING ASIC
TIMING GENERATOR
Figure 16. System Applications Diagram
APPLICATIONS INFORMATION Grounding and Decoupling Recommendations
The AD9844A is a complete Analog Front End (AFE) product for digital still camera and camcorder applications. As shown in Figure 16, the CCD image (pixel) data is buffered and sent to the AD9844A analog input through a series input capacitor. The AD9844A performs the dc restoration, CDS, gain adjustment, black level correction, and analog-to-digital conversion. The AD9844A's digital output data is then processed by the image processing ASIC. The internal registers of the AD9844A--used to control gain, offset level, and other functions--are programmed by the ASIC or microprocessor through a 3-wire serial digital interface. A system timing generator provides the clock signals for both the CCD and the AFE.
Internal Power-On Reset Circuitry
After power-on, the AD9844A will automatically reset all internal registers and perform internal calibration procedures. This takes approximately 1 ms to complete. During this time, normal clock signals and serial write operations may occur. However, serial register writes will be ignored until the internal reset operation is completed. Pin 43 (formerly RSTB on the AD9843 non-A) is no longer used for the reset operation. Toggling Pin 43 in the AD9844A will have no effect.
As shown in Figure 17, a single ground plane is recommended for the AD9844A. This ground plane should be as continuous as possible, particularly around Pins 25 through 39. This will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. All decoupling capacitors should be located as close as possible to the package pins. A single clean power supply is recommended for the AD9844A, but a separate digital driver supply may be used for DRVDD (Pin 13). DRVDD should always be decoupled to DRVSS (Pin 14), which should be connected to the analog ground plane. Advantages of using a separate digital driver supply include using a lower voltage (2.7 V) to match levels with a 2.7 V ASIC, reducing digital power dissipation, and reducing potential noise coupling. If the digital outputs (Pins 3-12) must drive a load larger than 20 pF, buffering is recommended to reduce digital code transition noise. Alternatively, placing series resistors close to the digital output pins may help reduce noise.
REV. 0
-15-
AD9844A
3V ANALOG SUPPLY 0.1 F 1.0 F 1.0 F SERIAL INTERFACE 3 0.1 F
DVSS DVDD2 VRB
48 47 46 45 44 43 42 41 40 39 38 37
(LSB) D0 1 D1 2 D2 D3 4 D4 D5 6 D6 7 D7 8 D8 D9 D10 (MSB) D11 DATA OUTPUTS 12
9 10 11 12 5 3
PIN 1 IDENTIFIER
36 35 34
AUX1IN AVSS AUX2IN 0.1 F 0.1 F 3V ANALOG SUPPLY 0.1 F CCD SIGNAL 0.1 F 0.1 F 0.1 F 3V ANALOG SUPPLY
AVDD2 33 BYP4
AD9844A
TOP VIEW (Not to Scale)
32 31 30
NC CCDIN
BYP2 29 BYP1
28
AVDD1 AVSS 26 AVSS
27 25 13 14 15 16 17 18 19 20 21 22 23 24
SHP SHD
DRVDD
DATACLK
CLPDM DVSS
DVSS PBLK CLPOB
DRVSS DVSS
DVDD1
NC = NO CONNECT 6 CLOCK INPUTS
3V DRIVER SUPPLY
0.1 F
0.1 F 3V ANALOG SUPPLY
Figure 17. Recommended Circuit Configuration for CCD-Mode
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead LQFP (ST-48)
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45)
0.354 (9.00) BSC SQ
48 1 37 36
TOP VIEW
(PINS DOWN)
0.276 (7.00) BSC SQ
25
COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09)
0 MIN
12 13 24
0.019 (0.5) BSC 7 0
0.011 (0.27) 0.006 (0.17) 0.057 (1.45) 0.053 (1.35)
0.006 (0.15) SEATING 0.002 (0.05) PLANE
-16-
REV. 0
PRINTED IN U.S.A.
C02195-0-10/00 (rev. 0)
THREE-STATE
SDATA SL
NC STBY NC
CML
SCK
VRT

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